One or more aspects relate, in general, to processing within a computing environment, and in particular, to the processing of string or array data within the computing environment.
String data is often scanned to find the first occurrence of a specific condition. For example, in a string compare, two strings are compared producing a result. The comparison is, e.g., a sequential comparison of corresponding characters from each string until a mismatched pair of characters is detected. The result of the string compare is the comparison of the mismatched pair of characters (e.g., less than, greater than, equal to). As a particular example, a set of data of a first string is loaded into a first register and a set of data of a second string is loaded into a second register. A compare is performed of the data in the two registers. A check is made as to whether a specific condition exists, such as a miscompare of corresponding characters from the two registers. If not, a status is set indicating that there are no miscompares, and the next sets of data are loaded into the registers and compared until the end of the strings. However, if the specific condition occurs within a set of data, such as a miscompare, then the next step is to determine the location of the condition.
Typically, for each pair of data sets compared, the compare operation produces a result of all zeros for that pair, if the compare indicates a false result, and all ones for the pair, if the compare indicates a true result relative to the predicate being compared. Then, a determination may be desired as to the location of an occurrence of the specific condition within the result, such as the first miscompare.
In making this determination, all the leading zeros in the result are counted until a non-zero value is reached, and that count is used to determine the location of the condition. However, while a hardware implementation of this is tolerable for general purpose registers (e.g., generally 64-bit or narrower), it is not tolerable when scanning larger, wider layouts, such as 128 bit registers, and beyond. This is especially true where the hardware implementation requires those registers to be split into 64 bit halves due to microarchitectural trade-offs and cycle time constraints. In this situation, it becomes difficult to implement such a bit count across the wide layout registers. Thus, this type of counting is not used in certain processing, like Single Instruction, Multiple Data (SIMD) processing of vector registers.